1. Field of the Invention
This invention relates in general to the design of integrated circuits (ICs) and in particular to designing IC layouts.
2. Description of the Related Art
In the design and manufacture of modem Integrated Circuits (ICs), a number of advanced technologies are applied in concert to achieve uniformity and fidelity of all the patterned IC features, including transistors. Such advanced technologies span computer-aided design tools, photomask design tools and fabrication equipment, as well as lithography tools in the foundry. In all of these technologies, the simulation model of the transistor is based on idealized transistor channel widths and lengths. The transistor channel is modeled for simulation purposes as a rectangle. Further, the physical realization of the transistor channel, as represented in a circuit designer's computer-aided layout tool, is again a rectangle, e.g., the rectangular region where a polysilicon shape overlaps a diffusion shape. Subsequently, reticle enhancement techniques (RETs), notably those including optical proximity correction (OPC), sub-resolution assist features (SRAFs) and phase-shifting masks (PSM), all aim to optimize a mask design so that the transistor shape printed on the wafer has maximum fidelity to the rectangular drawn or designed shape. To summarize, in the vast majority of IC design and manufacturing flows, transistors are modeled, designed, drawn and printed so that their gates have perfectly rectangular channels.
With modern deep-submicron or decananometer-scale IC manufacturing processes, a very serious problem is that of leakage current, and therefore leakage power dissipation. It has been projected that in 65 nm process technologies, up to half of the power consumption of an IC can be static power due to leakage mechanisms. Static power is also known as “useless” power since it is dissipated without achieving any advancement of useful computations by the circuit. Components of static power dissipation include subthreshold leakage current, gate leakage or direct tunneling current, junction leakage or tunneling current, hot carrier injection current, gate-induced drain leakage current, punch-through current, etc. Such currents can exhibit sensitivities to environmental or manufacturing process variations. For example, subthreshold leakage current grows exponentially with a decrease in transistor channel length.
Present-day IC design and manufacturing processes only draw, layout and manufacture uniformly rectangular devices that meet prescribed transistor channel dimensions. Therefore, today's IC design and manufacturing processes fail to exploit a valuable degree of freedom, whereby not only the length and width but more generally, the shape of the transistor channel can be optimized to achieve a target objective with respect to performance, power, reliability, manufacturing yield, and other metrics. Due to this failing, today's IC design and manufacturing processes suffer unnecessary loss of performance, power, reliability, and parametric yield in manufactured ICs.
There exists a need for a method and system and that can reshape the transistor channel to improve the performance and leakage power of manufactured ICs. The method and system should be capable of improving the reliability, manufacturing yield and parametric yield of manufactured ICs. The method and system should also be capable of being used within the existing IC design cycle, to improve the design of the IC and make use of existing and known circuit analysis tools.